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The W65C816S (also 65C816 or 65816) is a 16-bit microprocessor (MPU) developed and sold by the Western Design Center (WDC). Introduced in 1983,〔(Chronology of Microprocessors (1980-1989) )〕 the W65C816S is an enhanced version of the WDC 65C02 8-bit MPU, itself a CMOS enhancement of the venerable MOS Technology 6502 NMOS MPU. The ''65'' in the part's designation comes from its 65C02 compatibility mode, and the ''816'' signifies that the MPU has selectable 8– and 16–bit register sizes. In addition to the availability of 16 bit registers, the W65C816S features extended memory addressing to 24-bits, supporting up to 16 megabytes of random access memory, an enhanced instruction set, and a 16 bit stack pointer, as well as several new electrical signals for improved system hardware management. At reset, the W65C816S starts in "emulation mode," meaning it essentially behaves as a 65C02. Following reset, the W65C816S may be switched to "native mode" with a two instruction sequence, causing it to enable all enhanced features, yet still maintain a substantial degree of backward compatibility with most 65C02 software. However, unlike the PDIP40 version of the 65C02, which is a pin-compatible replacement for its NMOS ancestor, the PDIP40 W65C816S is not pin-compatible with any other 6502 family MPU. Related to the W65C816S is the no-longer-produced W65C802, which is discussed below. ==History== Development of the W65C816S commenced in 1982 after Bill Mensch, founder and CEO of WDC, as well as the designer of the 65C02 microprocessor, consulted with Apple Computer on a new version of the Apple II series of personal computers that would, among other things, have improved graphics and sound. Apple wanted an MPU that would be software compatible with the 6502 then in use in the Apple II but with the ability to address more memory, and to load and store 16 bit words. The result was the 65C816, finished in March 1984, with samples provided to both Apple and Atari. Apple subsequently integrated the 65C816 into the Apple IIGS computer. Mensch was aided during the design process by his sister Kathryn, who was responsible for part of the device's layout. In the 1990s, the 65C816 (as well as its antecedent, the 65C02) was converted to a fully static core, which made it possible to completely stop the processor clock without losing data in any of the registers. This feature, along with the use of asynchronous static RAM, made it possible to produce designs that used minimal power when in a standby state. The basic 65C816 design was second-sourced by GTE, Sanyo and others from the mid-to-late 1980s to the early 1990s. , the W65C816S is available from WDC in a 40 pin PDIP or PLCC44 package, as well as a core for ASIC integration (for example Winbond's W55V9x series of TV Edutainment ICs). WDC, itself a fabless semiconductor company, works with various foundries to produce the W65C816S, as well as other compatible products. Discrete processors are available through a number of electronics distributors. For designers who wish to include W65C816S functionality into a custom ASIC, WDC offers RTL (register-transfer level) code in Verilog. In the past, WDC offered a 65(C)02 PDIP40 pin-compatible variant of the W65C816S referred to as the W65C802. The 65C802 was fully compatible with the 65C02 in all respects, but was 100 percent software compatible with the 65C816, including the use of 16–bit registers. The W65C802 lacked the ability to generate a full 24-bit address, thus limiting it to 64 kilobytes of memory like the 65C02. The 65C802 was produced by WDC and GTE during the mid-to-late 1980s and early 1990s. Typically, when hardware manufacturers designed a project from the ground up, they used the 65C816 rather than the 65C802, resulting in the latter being withdrawn from production. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「WDC 65816/65802」の詳細全文を読む スポンサード リンク
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